package group

import chisel3._
import chisel3.util.RegEnable

class BUFG extends  BlackBox {
  val io = IO(new Bundle() {
    val I = Input(Clock())
    val O = Output(Clock())
  })
}

class Daisy_IO extends Bundle with chip_config {
  val cim_dcdata = Output(UInt(Daisy_BW.W))
  val cim_dcvld  = Output(Bool())
}

class card_IO extends Bundle with chip_config {
  val card_group_data = Input(UInt(DATA_BW.W))
  val card_group_cmd  = Input(Bool())
  val group_card_state= Output(Bool())
  val group_card_result = Output(UInt(RESULT_BW.W))
}
class transfer extends RawModule with chip_config {
  val io = IO(new Bundle{
    val systemclk = Input(Clock())
    val systemRstn = Input(Bool())
    val cardio    = new card_IO
    val emitterio = Flipped(new emitter_IO)
  })
  val systemRst = !io.systemRstn
  withClockAndReset(io.systemclk,systemRst){
    io.emitterio.fpga_cim_data := RegEnable(io.cardio.card_group_data,0.U,true.B)
    io.emitterio.fpga_cim_cmd  := RegEnable(io.cardio.card_group_cmd,false.B,true.B)
    io.cardio.group_card_result  := RegEnable(io.emitterio.cim_fpga_result,0.U,true.B)
    io.cardio.group_card_state   := RegEnable(io.emitterio.cim_fpga_state,false.B,true.B)
  }
}




